In order to remove fixed pattern noise which is generated by variation in reset potential of a floating diffusion (FD), and variation in threshold voltage of a pixel amplifying transistor, solid-state image sensors generally include a fixed-pattern-noise cancellation circuit (FPN cancellation circuit) for outputting the difference between an output potential of a vertical signal line when resetting the FD and an output potential of the vertical signal line when reading a signal, as an output signal.
FIG. 8 is a diagram showing a structure of a common fixed-pattern-noise cancellation circuit. As shown in the figure, in the common fixed-pattern-noise cancellation circuit (FPN cancellation circuit), a clamp capacitive element 1101 having a capacitance value C1, and a sampling capacitor 1102 having a capacitance value C2 are connected in series with each other at one end of a vertical signal line 1105. A node 1103 between the clamp capacitive element 1101 and the sampling capacitor 1102 is an output node of the FPN cancellation circuit, and a reference power supply for supplying a reference voltage Vclamp is connected to the node 1103 through a switch 1104 formed by a transistor.
The FPN cancellation circuit has two phases. First, in a first phase, the switch 1104 is turned on to apply the reference voltage Vclamp to the node 1103. At this time, an FD is reset in a pixel, and the potential on the vertical signal line 1105 becomes Vrst, which is an amplified signal of a reset potential of the FD. Thus, charge Q1, which is held in the clamp capacitive element 1101, becomes “C1×(Vrst−Vclamp),” and charge Q2, which is held in the sampling capacitor 1102, becomes “C2×Vclamp.”
Then, in a second phase, the switch 1104 is turned off. At this time, in the pixel, signal charge is transferred from a photodiode (PD) to the FD. Thus, the potential on the vertical signal line 1105 becomes Vsig, which is an amplified signal of the potential of the FD in the state where the signal charge generated in the PD has been transferred thereto. Provided that Vsh is a potential at the node 1103, charge Q1′, which is held in the clamp capacitive element 1101, becomes “C1×(Vsig−Vsh),” and charge Q2′, which is held in the sampling capacitor 1102, becomes “C2×Vsh.” Since the total electric charge at the node 1103 is conserved, Q1+Q2=Q′+Q2′. That is, the voltage Vsh at the node 1103 becomes “Vclamp−C1(Vrst−Vsig)/(C1+C2).”
Thus, a value, which is calculated by subtracting a product of the difference between the reset voltage Vrst and the signal voltage Vsig of the FD, and a voltage gain “C1/(C1+C2)” of the FPN cancellation circuit, from the reference voltage Vclamp, is an output voltage of the FPN cancellation circuit. Even if the value of Vrst varies, the magnitude of the amplitude of (Vrst−Vsig) does not vary. Thus, the use of the FPN cancellation circuit enables fixed pattern noise, which is generated by variation in Vrst, to be removed.
However, the use of this FPN cancellation circuit has a problem of black crushing, i.e., a problem that the pixel output becomes dark when a pixel receives bright light, such as sunlight and spotlight (“high-brightness black crushing”).
FIG. 9(a) is a diagram showing a structure of a pixel circuit and an FPN cancellation circuit in a conventional solid-state image sensor, and FIG. 9(b) is a timing chart showing a potential change of various control signals, and FD and Vsh in the conventional solid-state image sensor.
The problem resulting from incidence of bright light will be described below with reference to FIGS. 9(a) and 9(b). In a pixel which has received bright light, signal charge generated and accumulated by a PD has been saturated, and excess signal charge, generated by further light incidence on the PD, overflows from the PD to an FD. Thus, the FD potential decreases when, or right after, the FD in the pixel is reset to a predetermined potential in the FPN cancellation operation described above, and the potential on the vertical signal line 1105, which is an amplified signal of the decreased FD potential, is replaced with the reference potential Vclamp of the FPN cancellation circuit. Then, the signal charge is read from the PD to the FD. However, since the FD potential decreases only to a certain level, the amplitude of (Vrst−Vsig) decreases, and the signal level at the output node of the FPN cancellation circuit becomes lower than the saturation signal level, although the PD has been saturated. This causes black crushing, i.e., a problem that the output of a part, which received bright light, becomes dark (“high-brightness black crushing”). The problem resulting from the incidence of bright light was described above.
In order to prevent this problem, a technique of suppressing black crushing caused by incidence of bright light, is disclosed in a related art solid-state image sensor described in Patent Document 1. As shown in FIG. 10, this solid-state image sensor includes a bypass transistor 1115, which is provided in parallel with the clamp capacitor 1101 and receives a threshold voltage Vb at its gate electrode. Thus, when the voltage on the vertical signal line 1105 becomes lower than the voltage (Vb−Vth), the bypass transistor 1115 is turned on to write the voltage on the vertical signal line 1105 directly to the sampling capacitor 1102, thereby suppressing the black crushing due to the incidence of bright light.
Patent Document 1: Japanese Published Patent Application No. 2006-222708